(a) Field of the Invention
The present invention relates to a CAD (computer aided design) system for designing an ASIC (application specific integrated circuit) and, more particularly, to a CAD system which is capable of reducing a turn around time (TAT) for the design of an ASIC.
(b) Description of a Related Art
In a fabrication process for a semiconductor device such as ASIC, the technique for designing a system-on-chip LSI including therein a plurality of ICs integrated on a single chip is highlighted. In the field of LSIs for the communication use, the demands for integrating or embedding a higher-speed IC operating with a smaller voltage amplitude or a higher-resolution IC having a higher resolution and a higher-integrated IC operating at a lower speed in a single chip have drastically increased.
Examples of the higher-speed ICs include a logic circuit operating with a low voltage differential signaling (LVDS) and a current mode logic circuit (CML). Examples of the higher-integrated ICs include a CMOS device, which operates with a higher voltage amplitude between source potentials and consumes extremely small current during a waiting mode thereof.
Demands have also increased for designing the embedded LSI including the higher-speed IC and the higher-integrated IC with a smaller TAT. The embedded LSI generally includes in the higher-speed IC a plurality of basic cells each including device elements having a relatively large size, and in the higher-integrated IC a plurality of basic cells each having device elements having a relatively small size and thus occupying a smaller area.
FIG. 1 shows a CAD system used for designing a LSI such as an ASIC (Application Specific Integrated Circuit). The CAD system 11 includes an input section 12, a library storage 13, a data processor 14, a display panel 15 and an output section 16. In the CAD system, the data processor 14 operates for processing based on the circuit data or user data input through the input section 12 and the library data stored in the library storage 13, then generates custom mask pattern data in accordance with the requested specification, and delivers the custom mask pattern data through the output section 16. The custom mask pattern data is generated by using an interactive processing while observing the display panel 15.
FIG. 2 shows a flowchart of designing a macro block in the CAD system of FIG. 1. After data for the macro block are read out in step 412, the size of the macro block, or the number of basic cells to be arranged in row and column directions, is determined based on the read data in step 413, followed by an automated wiring step for designing interconnections in the macro block. The term xe2x80x9cmacro blockxe2x80x9d as used herein means a set of basic cells or functional cells operating for a specific function as a whole. The macro block is categorized into two types: a software macro block and a hardware macro block, the latter being capable of handling the logic signals at a higher speed compared to the former.
Examples of the hardware macro block include a first type having basic electric elements such as transistors, resistors and capacitors which are arranged and interconnected, and a second type having basic logic gates such as NANDs, NORs and flipflops in combination which are arranged and interconnected. The hardware macro block is generally implemented by the second type for achieving a higher-speed or higher-resolution operation. The data for hardware macro blocks are stored in the library storage of the CAD system after examination of the electric characteristics thereof including a timing characteristic. The data stored for the macro block in the library includes fixed information for the dimensions and external pins thereof. On the other hand, the data for software macro blocks in the library include interconnections between logic circuits, and does not include locational information for the elements and the interconnections.
In step 414, source lines for the semiconductor chip are fixed by an automated wiring technique, and basic cells are then located in step 415 by an automated arrangement technique, followed by automated wiring step 416 for the functional cells, and a subsequent verification step 417 for verifying the electric characteristics such as a timing characteristic. If the test results for the electric characteristics assure a desired operation, the steps for the macro block design are finished. If not, the process returns to step 412 or 413, for iterative processing for assuring the electric characteristics such as timings.
FIG. 3 shows a flowchart of a chip design in the CAD system of FIG. 1. In step 422, the macro block designing process of FIG. 2 is first conducted, then followed by input of the data for the semiconductor chip in step 423. In step 424, one or a plurality of hardware macro blocks are forcibly or manually arranged in a higher-integrated area.
In step 425, source lines for the chip are arranged by automated wiring, followed by automated arrangement of functional cells in the higher-integrated area in step 426, and automated wiring of signal interconnections between the functional cells in step 427. In step 428, electric characteristics of the resultant chip such as a timing characteristic are examined. If the test results assure the desired operation, the chip design is finished. If not, the process returns to step 422, 423 or 424 for iterative processing until desired characteristics can be obtained.
FIGS. 4 and 5 are detailed schematic flowcharts of a process shown in FIG. 2. After the process starts, interconnection information (netlist) 712 for the macro block, pin-arrangement information 713 and an automated arrangement/interconnection library 714 are read from the storage. In step 715, the size and shape of the hardware macro block are then determined for achieving a higher-speed operation based on the netlist 712, pin-arrangement information 713 and library 714, to obtain array information 716. FIG. 6 shows an example of the arrangement of resistors and bipolar transistors in one of the functional cells specified by the array information 716.
Subsequently, in step 717, source bus line information is added to the array information 716 of the hardware macro block by using an automated arrangement/wiring tool for the macro blocks, to thereby obtain enhanced array information 718. In step 719 of FIG. 5, the enhanced array information 718 is further added with data for type xe2x80x9cBxe2x80x9d (higher-speed) logic cells, which are manually arranged, to thereby obtain macro block arrangement data 720.
FIG. 6 shows the arrangement of a higher-speed (or type xe2x80x9cBxe2x80x9d) logic circuit disposed in a higher-speed area and FIG. 7 shows a circuit diagram for the logic circuit, which includes bipolar transistors and resistors as well as source lines and signal lines. The source lines include VCC source line, VCSI reference line and GND line. The logic circuit is implemented by a differential circuit or an ECL circuit.
Back to FIG. 5, in step 721, automated wiring is conducted in the ECL circuit based on the macro block information 720 to obtain macro block interconnection data 722. If desired interconnections are not obtained by the automated wiring step, a manual wiring function included in the automated arrangement/interconnection tool is used for correction of the interconnections obtained by the automated wiring steps. Then, in step 723, characteristics of the obtained macro blocks are examined based on the macro block interconnection data 722, followed by judgement of the test results in step 724 If it is judged that desired characteristics are obtained in the macro blocks, the process advances to step 725 or 727. If it is judged that desired characteristics are not obtained, the process returns to steps 741 and 742 for judgement whether or not correction in the interconnections is sufficient to allow the resultant macro block to pass the verification.
In step 725, an automated arrangement/interconnection library 726 is then generated based on the macro block interconnection data 22. This library 726 includes information for terminals and interconnection-prohibited area to be used in the automated arrangement/wiring tool as well as artwork information, thereby allowing the hardware macro block to be designed by a common design flow in common with other logic circuits.
In step 727, a delay library 728 is generated based on the circuit data including parasitic capacitances and parasitic resistances and extracted from the macro block interconnection data 722. The delay library 728 includes input/output conditions, delay data and rules for wiring between circuits to be used for a logic simulation. The order of the steps 725 and 727 may be reversed or these steps may be conducted concurrently.
In step 729, the automated arrangement/interconnection library 726 is embedded in the automated arrangement/wiring tool and evaluated therein. If it is judged in step 730 that the library 726 passes the evaluation, the process advances to step 731, and if not, the process advances to step 738. In step 731, libraries 726 and 728 are embedded in the CAD system 11 and evaluated therein. If it is judged in step 732 that libraries 726 and 728 pass the evaluation, the process advances to step 733, wherein libraries 726 and 728 are released from the output section to finish the macro block design. If it is judged in step 732 that libraries 726 and 728 do not pass the evaluation, the process advances to steps 736 and 737 to further judge as to whether a correction in the way of embedding into the CAD system is sufficient for the libraries 726 and 728 to pass the evaluation. If the judgement is affirmative, the process advances to step 735, wherein the way of the embedding into the CAD system 11 is corrected and the steps starting from step 723 are iterated. If the judgement is negative, then the process advances to step 738.
In steps 738 and 739, it is judged whether or not a correction of the library 726 is sufficient to pass the evaluation. If the judgement is affirmative, the process advances to step 740 wherein the library 726 is corrected to iterate the steps starting from step 729. If the judgement is negative, the process advances to steps 741 and 742, wherein correction of the interconnections is sufficient. If the judgement is affirmative, the process advances to step 743, wherein the interconnections are corrected to iterate the steps starting from step 723. If the judgement is negative, the process advances to steps 744 and 745, wherein it is judged whether or not correction in the arrangement of the type xe2x80x9cBxe2x80x9d logic circuit is sufficient.
In step 745, if the judgement is affirmative, the process advances to step 746, wherein the arrangement of the type xe2x80x9cBxe2x80x9d logic circuit (ECL circuit) is changed to iterate the steps starting from step 721. If the judgement is negative, the process advances to steps 747 and 748, wherein it is judged whether or not correction in the array information 716 is sufficient. If the judgement is affirmative, the process advances to step 749, wherein the array information 716 is corrected to iterate the steps starting from step 717. If the judgement is negative, the process advances to steps 750 and 751, wherein it is judged whether or not correction in the macro block is sufficient.
If the judgement is affirmative in step 751, the process advances to step 746, wherein the arrangement of the logic circuit is corrected to iterate the steps starting from step 721, whereas if the judgement is negative, the process advances to steps 753 and 754, wherein it is judged whether or not correction in the pin arrangement is sufficient. If the judgement is affirmative, the process advances to step 755, wherein the pin arrangement is corrected to iterate the steps starting from step 714. If the judgement is negative, the process advances to step 756, wherein the automated arrangement/interconnection library 715 is corrected to iterate the steps starting from step 715. It is to be noted that the process succeeding step 735 may be started at any step because the process corresponds to correction processing.
FIGS. 8 and 9 are detailed flowcharts for the chip design process shown in FIG. 3. After the process starts, netlist information 812 for the chip, pin-arrangement information 813 and automated arrangement/interconnection library 714 are read from the library storage. In step 815, macro blocks are forcibly or manually arranged to obtain arrangement data 816 by using the chip automated arrangement/wiring tool based on the netlist information 812, pin-arrangement information 813 and automated arrangement/interconnection library 714.
Subsequently, in step 817, source bus information is added to the arrangement data 816 by using the chip automated arrangement/interconnection tool to obtain enhanced macro block arrangement data 818. In step 819, logic gates are arranged in the enhanced macro block arrangement data 818 by using macro block automated arrangement/wiring tool to obtain chip arrangement data 820.
FIG. 10 shows an example of an functional cell xe2x80x9cCAxe2x80x9d implemented by a type xe2x80x9cAxe2x80x9d logic gate, which is capable of being higher integrated, and FIG. 11 shows the circuit diagram therefor. The functional cell CA includes source lines VDD and GND, between which an nMOSFET and a pMOSFET having diffused regions and gate electrodes are disposed. The gate electrodes are made of polysilicon, and the diffused regions may be called xe2x80x9cfieldsxe2x80x9d.
In step 821, automated wiring is conducted by using chip automated arrangement/wiring tool based on the chip arrangement data 820 to obtain chip arrangement/interconnection data 822. The process then advances to step 823 or 825 for evaluation of characteristics such as a timing characteristic. If desired interconnections are not obtained in the automated wiring step 821, the manual wiring function in the chip automated arrangement/wiring tool is used to correct the data 822. The order of the steps 823 and 825 may be selected arbitrarily or these steps may be conducted concurrently. However, step 823 is in general conducted first because the evaluation for the characteristics of the peripheral areas for the macro blocks are more strict.
In step 823, characteristics of the peripheral area for the macro block are evaluated by using actual interconnections based on the chip arrangement/interconnection data 822. If it is judged in step 824 that desired characteristics are obtained, the process advances to step 827 wherein mask data 828 is generated to finish the chip design process. If the judgement is negative, the process advances to steps 830 and 831, wherein correction in the interconnections is sufficient.
On the other hand, in step 825, characteristics of the type xe2x80x9cAxe2x80x9d logic circuit are evaluated using actual interconnections based on the arrangement/interconnection data 822 to judge in step 826 whether or not desired characteristics are obtained. If the judgement is affirmative, the process advances to step 827 wherein similar processing is conducted. If the judgement is negative, the process advances to step 830, wherein similar processing is conducted.
If the judgement is affirmative in step 831, the process advances to step 832, wherein the interconnections are corrected to iterate the steps starting from step 822. If the judgement is negative, the process advances to steps 833 and 834 wherein it is judged whether correction in the arrangement of the type xe2x80x9cAxe2x80x9d logic circuit is sufficient. If the judgement is affirmative in step 834, the process advances to step 835 wherein the arrangement of the type xe2x80x9cAxe2x80x9d logic circuit is corrected to iterate the steps starting from step 821. If the judgement is negative in step 834, the process advances to steps 836 and 837 wherein it is judged whether or not correction in the arrangement of the macro blocks is sufficient. If the judgement is affirmative in step 837, the process advances to step 838 wherein the arrangement of the macro block is corrected to iterate the steps starting from step 817. If the judgement is negative in step 837, the process advances to steps 839 and 840 wherein it is judged whether or not correction in the netlist is sufficient.
If the judgement is affirmative in step 840, the process advances to step 841, wherein the netlist 812 is corrected to iterate the steps starting from step 815. If the judgement is negative in step 840, the process advances to step 842 and 843 wherein it is judged whether or not correction in the pin arrangement is sufficient. If the judgement is affirmative in step 843, the process advances to step 844 wherein pin arrangement is corrected to iterate the steps starting from step 815. If the judgement is negative, the process advances to step 845 wherein the automated arrangement/interconnection library 814 is corrected to iterate the steps starting from step 815.
It is to be noted that, in the series of steps as described above, since the steps succeeding step 830 are conducted for correction, the order of the steps are not limited to the example as recited above. The correction steps are conducted by using an engineering change order (ECO) function, which allows the execution to be limited to the data to be corrected, by inputting the data before correction and after correction. If desired characteristics are not finally obtained by correction or change in the steps after step 830, the macro block design itself obtained by the netlist 812 is corrected.
In the conventional process, designing the embedded IC having a higher-integrated (type xe2x80x9cAxe2x80x9d) circuit section and a higher-speed (type xe2x80x9cBxe2x80x9d) circuit section is conducted by determining a hardware macro block implementing the higher-speed circuit section, forcibly or manually arranging the hardware macro block within the higher-integrated circuit area, and designing the whole chip area by the flowchart of FIG. 3, to obtain the chip design such as shown in FIG. 12.
In FIG. 12, the designed chip 30 includes a type xe2x80x9cAxe2x80x9d circuit area as a higher-integrated circuit area, a hardware macro block xe2x80x9cHMxe2x80x9d as a higher-speed circuit area disposed as a part of the internal cell area and shown by hatching, and I/O cell areas 31 disposed at the outer periphery of the chip. Ring-shaped source line AVR and ground line AGR are disposed as source/ground lines encircling the internal cell area, and ring-shaped source line BVR and ground line BGR are disposed as source/ground lines encircling the hardware macro block.
FIG. 13 shows detailed arrangement of a part of the hardware macro block shown in FIG. 12. The hardware macro block generally includes a plurality of basic cells 33 and 34 in underlying data and a plurality of primitive functional cells 35 in overlying data. The primitive functional cells 35 are generally arranged automatically by the automated arrangement/wiring tool based on the circuit data, whereas the macro block having a higher operational speed or a higher resolution is manually arranged at an optimum location. The hardware macro block xe2x80x9cHMxe2x80x9d includes a basic cell array, wherein arrangement of a column of basic cells are inverse of that of the adjacent column. The designer inputs circuit data by using a mouse while observing the display panel in FIG. 1 to locate the functional cells 35 prepared beforehand for the macro block. Thus, higher-speed logic gates such as CML are arranged, followed by wiring between the functional cells by using automated wiring technique.
The timing verification between the input terminals and output terminals of the macro block after automated wiring is conducted based on a simulation library of the static timing analysis prepared for the macro block design, while specifying the input terminals of input stage functional cells and the output terminals of output stage functional cells of the macro block. If detailed verification is required, the artwork data is converted to netlist information, circuit data in SPICE format, by a layout parameter extraction tool, and the delays between the inputs and the outputs of the macro block are obtained by comparison.
In the conventional technique for the embedded LSI as described, there is a drawback of a large TAT wherein the design for the embedded LSI is obtained by the two-step design process including the macro block design and the overall chip design. If the chip design involves a defect in a timing verification after the chip arrangement/wiring step, the design for the hardware macro block must be corrected after returning to the initial design stage for the macro block.
Especially in the design for the macro block shown in FIG. 2, the hardware macro block and the library therefor are designed after the floor planning of the chip. In this case, chip size, pin arrangement, terminal location, circuit scale for the higher-speed circuit section, and the location and the arrangement of the hardware macro block must be separately determined for obtaining a higher-speed circuit suited for the type of the embedded LSI.
On the other hand, in the chip design shown in FIG. 3, since the size of the hardware macro block is fixed in the internal area, the optimum locations for the terminals are difficult to obtain. Thus, addition of buffers is generally necessary between the higher-speed circuit section and the input/output buffers or between the higher-speed circuit section and the higher-integrated circuit section for a timing adjustment. The addition of the buffer as well as addition of the interconnections for the buffer increases the design TAT for the product and increases the power dissipation in the embedded LSI.
It is therefore an object of the present invention to provide a design technique for the embedded LSI, which is capable of designing an optimum circuit arrangement in the embedded LSI for each type of the LSI and reducing the design TAT for the development of the embedded LSI.
The present invention provides a method for designing a LSI by using a CAD system including the steps of defining an internal cell area on a chip, the internal cell area having a first site definition for receiving a first-type logic cells, disposing a flexible macro block in a first area of the internal cell area based on flexible macro block information, changing a site definition of the first area from the first site definition to a second site definition for receiving a second-type logic cells, arranging respective logic cells in the first area for the flexible macro block and in a second area of the internal cell area in accordance with the second site definition and the first site definition, respectively, forming interconnections between the basic cells to form a first circuit section and a second circuit section, respectively, from the first area for the flexible macro bock and the second area, separately evaluating electric characteristics of the first circuit section and the second circuit section, and separately correcting the first circuit section and the second circuit section based on results of the evaluation and correction of.
In accordance with the method of the present invention, the design for arrangement/interconnections of the logic gates can be conducted parallel to each other, with minor corrections including changing the site definitions between the first site definition and the second site definition based on the change of the arrangement of the flexible macro block, which is changed based on the results of evaluation of the electric characteristics of the flexible macro block and the vicinity thereof.